Conventionally, plural bonding pads to electrically connect internal circuits thereof to external are disposed along an outer periphery of a surface in a semiconductor chip.
External terminals such as a lead frame are connected to these bonding pads by, for example, bonding wires made of gold by a predetermined assembly process.
Besides, the bonding pad also functions as an abutting portion to bring probe needles of a tester into contact when an electrical inspection such as a characteristic test of the semiconductor chip is performed in addition to function as the pad to connect the bonding wire. In this case, a scratch called as a probe trace remains at a surface of the bonding pad when the probe needles of the tester are brought into contact with the bonding pad to perform the electrical inspection.
In recent years, requirements for higher integration and higher function arise for the semiconductor device, and miniaturization of the semiconductor chip is required and more electrodes are provided on the semiconductor chip. It is necessary to provide more bonding pads within a limited region at the surface of the semiconductor chip to correspond to the above requirements.
However, in this case, there is a problem in which the electrical connection of the probe needles with the bonding pad becomes insufficient when the region of the bonding pad is reduced because the probe trace at the surface of the bonding pad protrudes out of the bonding pad.
For example, a method in which the bonding pads are disposed at an input/output circuit region of a circuit region to secure region for the bonding pads is employed in Patent Document 1 corresponding to the aforementioned problem. Further, there also is a method in which a part of the bonding pads is formed to protrude out of the input/output circuit region, to further secure the region of the bonding pads for in Patent Document 2.
Recently, requirements for high integration, high function of a semiconductor device arise more and more, and for example, it is proposed that bonding pads are formed by arranging in parallel in two rows as in Patent Document 3. Incidentally, a case when the bonding pads are formed in one row is exemplified in FIG. 3, and a case when the bonding pads in one row are rearranged alternately is exemplified in FIG. 5 and FIG. 6 in the Patent Document 1.
The Patent Document 1 in which the above-stated various constitutions are disclosed is applied to the Patent Document 2 (,3), and thereby, a constitution is conceivable in which I/O cells where the bonding pads are disposed are arranged in two rows at the input/output circuit region. However, in this case, lengths of the bonding wires to be connected become significantly uneven, by each row and characteristic deterioration of an integrated circuit of the semiconductor chip occurs resulting from the distance difference of the bonding wires. Besides, in this case, there is a problem in which disposed states of probe needles of a tester become uneven by each row, and characteristic difference (difference of L, R, C, L indicates inductance, R indicates resistance, C indicates capacitance) occurs in the probe needles resulting from the unevenness, and an accurate inspection result cannot be obtained.    Patent Document 1: Japanese Laid-open Patent Publication No. 11-307601    Patent Document 2: International Publication Pamphlet No. WO2004/93191    Patent Document 3: Japanese Laid-open Patent Publication No. 9-246314